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Manchester Seminar


On May 1, 2008, Dr Anderson is giving a seminar on the Perspex Machine in the School of Computer Science at the University of Manchester England.

The Perspex machine is a geometrical computer that is Turing complete. It operates in a space of transreal numbers. Finite versions of the machine can be implemented using conventional, digital, fabrication techniques. The machine is massively parallel at instruction level. It supports the pipelining of entire programs, including branches and non-recursive subroutines. A fully pipelined program produces one result after the pipeline latency, i.e. after the execution time of a single pass through the program. It produces one further answer on each subsequent clock tick. This makes it very well suited to repetitive numerical programs, such as Computational Fluid Dynamics, signal processing, cryptanalysis, and the like. The pipeline is limited by the number of Perspex processing elements. It is thought that 4 000 processing elements, or more, can be fabricated on a single chip. Each processing element is, roughly, equivalent to one line of a C program.

The seminar is in three parts. Part 1 is a brief introduction to transreal numbers. These numbers provide a total system of arithmetic. IEEE floating-point arithmetic is also total, but it will be criticised on the grounds that the behaviour of NaN is dangerous, and that all of the behaviour of "minus zero" can be obtained, efficiently, by other means, even in an IEEE compliant processor.

Part 2 of the seminar is a discussion of approximate execution of programs. The Turing machine supports approximate execution to the extent that similarity of input tapes implies similarity of output tapes. There will be a discussion of what makes contemporary processors more fragile than the Turing machine. The 4D Perspex machines will be presented as examples of robust processors. These machines support approximate execution geometrically. An example will be given of a program that continues to produce approximate answers, even after deletion of 90% of its instructions.

Part 3 of the seminar is a discussion of practical Perspex machines. The 2D Perspex machines can be fabricated in the surface of a silicon chip. Some of them have been implemented in FPGA and in functional simulators. They support the usual software stack of loaders, assemblers, compilers, and user programs. Open design issues concerning practical Perspex machines will be presented. The 2D Perspex machine has a peak power requirement that is the square root of the number of processors, but it is not known if it is feasible to fabricate this power model. The Perspex machine has no memory wall, but it is not known what bandwidth of I/O can feasibly be fabricated. It appears that this bandwidth is greater than 300 M words per second, so that at least 300 000 000, 64-bit floating-point results can be returned per second, if the direction of I/O is switchable. It is not known what limits there are on clock-distribution within and between Perspex chips, though it is known that the Perspex machine can be run asynchronously with a code density penalty of about 30%.

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James A. D. W. Anderson 2008

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Last updated17 March 2009